An Ultra Low-Power RFIC Chip for Wireless and Communication Applications, PI: A/P Yeo Kiat Seng, NTU

Silicon is believed to be the most suitable material, satisfying the demands of the rapidly growing wireless and communication market through low fabrication cost and ease of achieving SoC or SiP integration with RF front-end and digital/analogue baseband co-existing on the same chip or in a common package, respectively. Nonetheless, tough challenges lie ahead for RFIC designers when they choose to develop their wireless and communication integrated circuits using silicon technologies.

The current deep-submicron CMOS processes continue to use conductive silicon substrates predominantly for latch-up immunity under tighter design rules. Integrated inductors, transistors and circuit interconnects fabricated on such lossy substrate suffer from undesirable energy dissipation in terms of capacitive and magnetic losses. In addition, high resistive loss of aluminum and copper metal lines at giga-hertz frequency range not only further degrade the performance of the inductors but introduces more design difficulties as circuit designers and engineers need to carefully consider the effects of the circuit interconnects at GHz. Moreover, at very small technology nodes, device modeling at giga-hertz frequency range becomes a big challenge due to the large variations of process parameters. More specifically, RF circuits and systems fabricated in such an environment are more sensitive to changes in the process parameters and/or technologies. Also, current commercial EDA tools are unable to predict substrate coupling effect at GHz range.

In this project, there is another big challenge of designing a high performance RF chip to operate in a low power supply voltage environment. A low power supply voltage is needed for ultra low-power consumption requirements and extending of the battery life for portable applications. However, it is a well known fact that under a scaled down supply voltage, the delay of a circuit will increase tremendously. There are also issues of our RF chip causing interferences to nearby medical equipment and existing wireless and communication signals interfering with our RF chip. Without in-depth studies and good solutions to address these challenges, RFIC designers and engineers will have to rely on many costly and time-consuming design iterations before they can succeed in delivering a RF CMOS circuit and/or system capable of satisfying the desired project specifications.

In order to achieve a significant reduction of power consumption, the RF chip can be improved in two aspects, circuits and systems. At the circuits and systems level, for example, typical CMOS RF transceivers designed for short range applications of less than 200 m would consume a few tens of milliamperes from a 3 V supply voltage using a standard CMOS process. The RF circuits are commonly designed to operate in the saturation region. The current consumption of the device can be reduced by an order of magnitude if it operates in the sub-threshold region. This can be done with a good model of the device in the sub-threshold region and good techniques for optimizing the speed and noise performance. As another example, the phase locked loop is an RF mixed signal sub-system of the transceiver. The power consumption of this sub-system can also be reduced significantly with the combination of the sub-threshold design and the optimization of switching activities in the circuits. Here we expect that a power reduction of an order of magnitude can be obtained with a combination of sub-threshold circuit design, design of digital building blocks with less switching activities and no short circuits paths, asynchronous design, and efficient signal processing soft-wares, etc.

Currently the above mentioned methodologies are being pursued by individual researchers without a concerted effort. The individual technologies are not shared for a common larger goal. However, all these designs and technologies will soon be developed at NTU as parts of a common goal of reducing the power consumption of the RF chip.