MPC on a Chip

The proposed project for EHS Phase II is a continuing effort from EHS Phase I [1] to realize the vision of “MPC on a Chip” for embedded control of high-bandwidth and/or miniaturized devices such as System-on-Chip (SoC). We believe the “MPC on a Chip” vision can be achieved with our intimate understanding of the MPC algorithm and through application specific customization of the hardware and software platform for each MPC application.

There are two main objectives in this Phase II project:

Model Predictive Control (MPC) has become an established control technology in the petrochemical industry. Its use is currently being pioneered in an increasingly wide range of high bandwidth applications, such as ships [2], aerospace [3, 4], road vehicles [5] and “Lab-on-Chip” devices[6].

MPC outperforms other control strategies through its ability to deal with constraints [7]. This requires on-line optimization, hence computational complexity can become an issue when applying MPC to complex systems with fast response times or to embedded applications where computational resource may be a major constraints. The Phase I study revealed also the need for a scalable and low-cost embedded control solution for “lab-on-chip” devices on which the number of actuators and sensors could be large.

Centralized MPC scales poorly with the size of the system (e.g. the number of actuators and sensors on a “lab-on-chip” device. Centralized MPC of large-scale systems is also viewed by most practitioners as highly unrealistic, even undesirable. To address this problem, various techniques to build decentralized or cooperative MPC has been proposed [8, 9, 10]. It is well known that a decentralized control approach can cause unacceptable closed-loop behaviour when the subsystems are tightly coupled. The key point is that, when decisions are made in a decentralized fashion, the actions of each sub-MPC must be consistent with those of other sub-MPCs, so that decisions taken independently do not lead to a violation of the coupling constraints. The decentralization of the control is further complicated when disturbances act on the subsystems making the prediction of future behaviour uncertain.

In Phase I, a new version of MPC named Multiplexed MPC was proposed [11]. The multiplexed MPC scheme solves the MPC problem for each subsystem sequentially, and updates subsystem controls as soon as the solution is available, thus distributing the control moves over a complete update cycle. The resulting computational speed-up allows faster response to disturbances, and hence improves performance, despite finding suboptimal solutions to the original problem. The multiplexed MPC scheme is also closer to industrial practice in many cases. We also obtained initial stability results for two variants of multiplexed MPC. This gives a theoretical foundation for the proposed multiplexed MPC strategy. We believe that the time multiplexed version of MPC opens up many opportunities to applying MPC to embedded and high bandwidth applications, such as “lab-on-chip” devices, autonomous guidance of a fleet of miniaturized land and aerial vehicles. Continuing research in this direction to make MPC scalable is necessary.

The encapsulation of the MPC algorithms as suitable modules for embedded control was also investigated in Phase I. A Handel-C model of MPC algorithm was created which could be synthesized and implemented as FPGA module [12]. This allows us to investigate the time-area trade-offs in implementing embedded MPC. We have also used software packages such as Matlab/Simulink, Handel-C, Xilinx ISE, etc to take a MPC solution from design to embedded implementation. Further work in this direction is required to achieve a higher level of automation to facilitate the embedded system community to explore the design space available in realizing a customized embedded MPC design.

Although the solution of the constrained optimization is shown to be piecewise affine in regions determined by the constraints [13], the number of such regions grow exponential with the complexity of the applications. In order to solve comparatively complex problems, we proposed instead customizable hardware and software to address application specific challenges in realizing embedded MPC solutions. This is very appropriate for SoC applications, where customized computational architecture could be built. An embedded MPC with reduced precision and customized data path could achieve orders of magnitude improvement over conventional techniques. The power and area savings through customized hardware, combined with higher clock cycles, would hopefully make embedded MPC cost effective.

A high level analysis of MPC code revealed that the computational algorithm consist mostly of repetitive matrix operations. One possibility of achieving low-power, small chip area and real-time embedded MPC is to have a modest microcontroller core acting as a host processor together with a customized matrix processor which acts as a hardware accelerator for the required matrix operations. We plan to investigate approaches suggested in [14], to explore efficient hardware implementation of MPC algorithm in which a wide variety of finite precision representations for different sizes are used in different internal variable. The partitioning of MPC into host processor and custom-made processor is another possibility to achieve time-area trade-offs.

In summary, although design techniques for multiplexed and decentralized cooperative MPC algorithms which guaranteed certain performance properties are available, however, to enable quick and flexible deployment of embedded MPC technology, basic computational blocks that could be re-used and re-configured to form customized MPC solutions that meet the power/chip area/timing requirements would be necessary. Thus, in this project, we aim to develop design methodologies which would encapsulate our know-how gained in EHS Phase I, to make MPC more accessible to the embedded system community. A framework for the development of low-power and small-chip area real-time embedded MPC implementations, based on co-operative design of hardware and software will be investigated. Ultimately, we hope to provide methodologies and tools to enable researchers and practitioners in embedded reactive system design to customize and optimize solutions for their own embedded MPC applications.

RECRUITMENT

  - Postdocs / RFs

  - RAs / REs / POs